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ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
36Mb QDRTMII SRAM 2-WORD BURST
FEATURES
* DLL circuitry for accurate output data placement
MT54W4MH8B MT54W4MH9B MT54W2MH18B MT54W1MH36B
Figure 1 165-Ball FBGA
* Separate independent read and write data ports with concurrent transactions * 100 percent bus utilization DDR READ and WRITE operation * Fast clock to valid data times * Full data coherency, providing most current data * Two-tick burst counter for low DDR transaction size * Double data rate operation on read and write ports * Two input clocks (K and K#) for precise DDR timing at clock rising edges only * Two output clocks (C and C#) for precise flight time and clock skew matching--clock and data delivered together to receiving device * Single address bus * Simple control logic for easy depth expansion * Internally self-timed, registered writes * +1.8V core and HSTL I/O * Clock-stop capability * 15mm x 17mm, 1mm pitch, 11 x 15 grid FBGA package * User-programmable impedance output * JTAG boundary scan
VALID PART NUMBERS
PART NUMBER MT54W4MH8BF-xx MT54W4MH9BF-xx MT54W2MH18BF-xx MT54W1MH36BF-xx DESCRIPTION 4 Meg x 8, QDRIIb2 FBGA 4 Meg x 9, QDRIIb2 FBGA 2 Meg x 18, QDRIIb2 FBGA 1 Meg x 36, QDRIIb2 FBGA
OPTIONS
* Clock Cycle Timing 4ns (250 MHz) 5ns (200 MHz) 6ns (167 MHz) 7.5ns (133 MHz) * Configurations 4 Meg x 8 4 Meg x 9 2 Meg x 18 1 Meg x 36 * Package 165-ball, 15mm x 17mm FBGA
NOTE:
MARKING1
-4 -5 -6 -7.5
MT54W4MH8B MT54W4MH9B MT54W2MH18B MT54W1MH36B F
1. A Part Marking Guide for the FBGA devices can be found on Micron's Web site--http://www.micron.com/numberguide.
The Micron(R) QDRTMII (Quad Data RateTM) synchronous, pipelined burst SRAM employs high-speed, lowpower CMOS designs using an advanced 6T CMOS process. The QDR architecture consists of two separate DDR (double data rate) ports to access the memory array. The read port has dedicated data outputs to support READ operations. The write port has dedicated data inputs to support WRITE operations. This architecture eliminates the need for high-speed bus turnaround. Access to each port is accomplished using a common address bus. Addresses for reads and writes are latched on rising edges of the K and K# input clocks, respectively. Each address location is associated with two words that burst sequentially into or out of the device.
GENERAL DESCRIPTION
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev. 9/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
PRODUCTS
AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
GENERAL DESCRIPTION (continued)
Since data can be transferred into and out of the device on every rising edge of both clocks (K and K#, C and C#), memory bandwidth is maximized while system design is simplified by eliminating bus turnarounds. Depth expansion is accomplished with port selects for each port (read R#, write W#), which are received at K rising edge. Port selects permit independent port operation. All synchronous inputs pass through registers controlled by the K or K# input clock rising edges. Active LOW byte writes (BWx#) permit byte or nibble write selection. Write data and byte writes are registered on the rising edges of both K and K#. The addressing within each burst of two is fixed and sequential, beginning with the lowest and ending with the highest address. All synchronous data outputs pass through output registers controlled by the rising edges of the output clocks (C and C# if provided, otherwise K and K#). Four balls are used to implement JTAG test capabilities: test mode select (TMS), test data-in (TDI), test clock (TCK), and test data-out (TDO). JTAG circuitry is used to serially shift data to and from the SRAM. JTAG inputs use JEDEC-standard 1.8V I/O levels to shift data during this testing mode of operation. The SRAM operates from a +1.8V power supply, and all inputs and outputs are HSTL-compatible. The device is ideally suited for applications that benefit from a high-speed, fully-utilized DDR data bus. Please refer to Micron's Web site (www.micron.com/ sramds) for the latest data sheet.
READ/WRITE OPERATIONS
All bus transactions operate on an uninterruptable burst of two data, requiring one full clock cycle of bus utilization. The resulting benefit is that short data transactions can remain in operation on both buses provided that the address rate can be maintained by the system (2x the clock frequency). READ cycles are pipelined. The request is initiated by asserting R# LOW at K rising edge. Data is delivered after the rising edge of K# (t + 1) using C and C# as the output timing references or using K and K#, if C and C# are tied HIGH. If C and C# are tied HIGH, they may not be toggled during device operation. Output tri-stating is automatically controlled such that the bus is released if no data is being delivered. This permits banked SRAM systems with no complex OE timing generation. Back-to-back READ cycles are initiated every K rising edge.
Figure 2 Functional Block Diagram: 2 Meg x 18
n
ADDRESS R# W#
K K#
n ADDRESS REGISTRY & LOGIC
W# BW0# BW1# D (Data In) R#
K K# 18 DATA REGISTRY & LOGIC 36 WR RE IG T E2 WD RR II TV EE R 2 n x 36 MEMORY ARRAY S EA NM SP ES 36 MUX RO EU GT P AU T C C, C# or K, K# 36 O U T P U T S E L E C T O U T P U T B U F F E R 18
Q (Data Out)
2
K
CQ, CQ# (Echo Clock Out)
NOTE: 1. The functional block diagram illustrates simplified device operation. See truth table, ball descriptions, and timing diagrams for detailed information. The x8, x9, and x36 operations are the same, with apporpriate adjustments of depth and width. 2. n = 20
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
READ/WRITE OPERATIONS (continued)
WRITE cycles are initiated by W# LOW at K rising edge. The address for the WRITE cycle is provided at the following K# rising edge. Data is expected at the rising edge of K and K#, beginning at the same K that initiated the cycle. Write registers are incorporated to facilitate pipelined, self-timed WRITE cycles and to provide fully coherent data for all combinations of reads and writes. A read can immediately follow a write, even if they are to the same address. Although the write data has not been written to the memory array, the SRAM will deliver the data from the write register instead of using the older data from the memory array. The latest data is always utilized for all bus transactions. WRITE cycles can be initiated on every K rising edge.
PROGRAMMABLE IMPEDANCE OUTPUT BUFFER
The QDR SRAM is equipped with programmable impedance output buffers. This allows a user to match the driver impedance to the system. To adjust the impedance, an external precision resistor (RQ) is connected between the ZQ ball and VSS. The value of the resistor must be five times the desired impedance. For example, a 350W resistor is required for an output impedance of 70W . To ensure that output impedance is one-fifth the value of RQ (within 15 percent), the range of RQ is 175W to 350W . Alternately, the ZQ ball can be connected directly to VDDQ, which will place the device in a minimum impedance mode. Output impedance updates may be required because variations may occur over time in supply voltage and temperature. The device samples the value of RQ. Impedance updates are transparent to the system; they do not affect device operation, and all data sheet timing and current specifications are met during an update. The device will power up with an output impedance set at 50W . To guarantee optimum output driver impedance after power-up, the SRAM needs 1,024 cycles to update the impedance. The user can operate the part with fewer than 1,024 clock cycles, but optimal output impedance is not guaranteed.
PARTIAL WRITE OPERATIONS
BYTE WRITE operations are supported, except for the x8 devices in which nibble write is supported. The active LOW byte write controls, BWx# (NWx#), are registered coincident with their corresponding data. This feature can eliminate the need for some READ-MODIFY-WRITE cycles, collapsing it to a single BYTE/NIBBLE WRITE operation in some instances.
Figure 3 Application Example
SRAM #1
Vt R D SA B RWW ## # ZQ Q C C# K K# R = 250 D SA
SRAM #4
B RWW ## # ZQ Q C C# K K#
R = 250
DATA IN DATA OUT Address Read# BUS Write# MASTER BW#
R
Vt Vt
(CPU or ASIC)
Source K Source K# Delayed K Delayed K# R R = 50 Vt = VREF/2
NOTE: In this approach, the second clock pair drives the C and C# clocks but is delayed such that return data meets data setup and hold times at the bus master.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
CLOCK CONSIDERATIONS
This device utilizes internal delay-locked loops for maximum output data valid window. It can be placed into a stopped-clock state to minimize power with a modest restart time of 1,024 clock cycles. Circuitry automatically resets the DLL when the absence of input clock is detected. See Micron Technical Note TN54-02 for more information on clock DLL start-up procedures.
DEPTH EXPANSION
Port select inputs are provided for the read and write ports. This allows for easy depth expansion. Both port selects are sampled on the rising edge of K only. Each port can be independently selected and deselected and does not affect the operation of the opposite port. All pending transactions are completed prior to a port deselecting. Depth expansion requires replicating R# and W# control signals for each bank if it is desired to have the bank independent of READ and WRITE operations.
SINGLE CLOCK MODE
The SRAM can be used with the single K, K# clock pair by tying C and C# HIGH. In this mode, the SRAM will use K and K# in place of C and C#. This mode provides the most rapid data output but does not compensate for system clock skew and flight times.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
4 MEG x 8 BALL ASSIGNMENT (TOP VIEW) 165-BALL FBGA
1 A B C D E F G H J K L M N P R
NOTE: 1. 2. 3. 4. 5. Expansion address: 2A for 72Mb NW1# controls writes to D4:D7 Expansion address: 7A for 144Mb Expansion address: 5B for 288Mb NW0# controls writes to D0:D3
2 VSS/SA1 NC NC D4 NC NC D5 VREF NC NC Q6 NC D7 NC TCK
3 SA NC NC NC Q4 NC Q5 VDDQ NC NC D6 NC NC Q7 SA
4 W# SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
5 NW1#2 NC/SA4 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA
6 K# K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C#
7 NC/SA3 NW0#5 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA
8 R# SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA
10 SA NC NC NC D2 NC NC VREF Q1 NC NC NC NC NC TMS
11 CQ Q3 D3 NC Q2 NC NC ZQ D1 NC Q0 D0 NC NC TDI
CQ# NC NC NC NC NC NC DLL# NC NC NC NC NC NC TDO
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
4 MEG x 9 BALL ASSIGNMENT (TOP VIEW) 165-BALL FBGA
1 A B C D E F G H J K L M N P R
NOTE: 1. 2. 3. 4. Expansion address: 2A for 72Mb Expansion address: 7A for 144Mb Expansion address: 5B for 288Mb BW0# controls writes to D0:D8
2 VSS/SA1 NC NC D5 NC NC D6 VREF NC NC Q7 NC D8 NC TCK
3 SA NC NC NC Q5 NC Q6 VDDQ NC NC D7 NC NC Q8 SA
4 W# SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
5 NC NC/SA3 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA
6 K# K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C#
7 NC/SA2 BW0#4 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA
8 R# SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA
10 SA NC NC NC D3 NC NC VREF Q2 NC NC NC NC D0 TMS
11 CQ Q4 D4 NC Q3 NC NC ZQ D2 NC Q1 D1 NC Q0 TDI
CQ# NC NC NC NC NC NC DLL# NC NC NC NC NC NC TDO
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
2 MEG x 18 BALL ASSIGNMENT (TOP VIEW) 165-BALL FBGA
1 A B C D E F G H J K L M N P R
NOTE: 1. 2. 3. 4. 5. Expansion address: 2A for 144Mb BW1# controls writes to D9:D17 Expansion address: 7A for 288Mb Expansion address: 10A for 72Mb BW0# controls writes to D0:D8
2 VSS/SA1 Q9 NC D11 NC Q12 D13 VREF NC NC Q15 NC D17 NC TCK
3 SA D9 D10 Q10 Q11 D12 Q13 VDDQ D14 Q14 D15 D16 Q16 Q17 SA
4 W# SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
5 BW1#2 NC SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA
6 K# K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C#
7 NC/SA3 BW0#5 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA
8 R# SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
9 SA NC NC NC NC NC NC VDDQ NC NC NC NC NC NC SA
10 VSS/SA4 NC Q7 NC D6 NC NC VREF Q4 D3 NC Q1 NC D0 TMS
11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
CQ# NC NC NC NC NC NC DLL# NC NC NC NC NC NC TDO
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
1 MEG x 36 BALL ASSIGNMENT (TOP VIEW) 165-BALL FBGA
1 A B C D E F G H J K L M N P R
NOTE: 1. 2. 3. 4. 5. 6. 7. Expansion address: 2A for 288Mb Expansion address: 3A for 72Mb BW2# controls writes to D18:D26 BW1# controls writes to D9:D17 Expansion address: 10A for 144Mb BW3# controls writes to D27:D35 BW0# controls writes to D0:D8
2 VSS/SA1 Q18 Q28 D20 D29 Q21 D22 VREF Q31 D32 Q24 Q34 D26 D35 TCK
3 NC/SA2 D18 D19 Q19 Q20 D21 Q22 VDDQ D23 Q23 D24 D25 Q25 Q26 SA
4 W# SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
5 BW2#3 BW3#6 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA
6 K# K SA VSS VSS VSS VSS VSS VSS VSS VSS VSS SA C C#
7 BW1#4 BW0#7 SA VSS VSS VDD VDD VDD VDD VDD VSS VSS SA SA SA
8 R# SA VSS VSS VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VSS VSS SA SA
9 SA D17 D16 Q16 Q15 D14 Q13 VDDQ D12 Q12 D11 D10 Q10 Q9 SA
10 VSS/SA5 Q17 Q7 D15 D6 Q14 D13 VREF Q4 D3 Q11 Q1 D9 D0 TMS
11 CQ Q8 D8 D7 Q6 Q5 D5 ZQ D4 Q3 Q2 D2 D1 Q0 TDI
CQ# Q27 D27 D28 Q29 Q30 D30 DLL# D31 Q32 Q33 D33 D34 Q35 TDO
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
FBGA BALL DESCRIPTIONS
SYMBOL SA TYPE Input DESCRIPTION Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K for READ cycles and K# for WRITE cycles. See Ball Assignment figures for address expansion inputs. All transactions operate on a burst of two words (one clock period of bus activity). These inputs are ignored when both ports are deselected. Synchronous Read: When LOW, this input causes the address inputs to be registered and a READ cycle to be initiated. This input must meet setup and hold times around the rising edge of K. Synchronous Write: When LOW, this input causes the address inputs to be registered and a WRITE cycle to be initiated. This input must meet setup and hold times around the rising edge of K. Synchronous Byte Writes (or Nibble Writes on the x8): When LOW, these inputs cause their respective Bytes to be registered and written if W# had initiated a WRITE cycle. These signals must meet setup and hold times around the rising edges of K and K# for each of the two rising edges comprising the WRITE cycle. See Ball Assignment figures for signal to data relationships. Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. Output Clock: This clock pair provides a user-controlled means of tuning device output data. The rising edge of C is used as the output timing reference for second output data. The rising edge of C# is used as the output reference for first output data. Ideally, C# is 180 degrees out of phase with C. C and C# may be tied HIGH to force the use of K and K# as the output reference clocks instead of having to provide C and C# clocks. If tied HIGH, these inputs may not be allowed to toggle during device operation. IEEE 1149.1 Test Inputs: 1.8V I/O levels. These balls may be left as No Connects if the JTAG function is not used in the circuit. IEEE 1149.1 Clock Input: 1.8V I/O levels. This ball must be tied to VSS if the JTAG function is not used in the circuit. HSTL Input Reference Voltage: Nominally VDDQ/2, but may be adjusted to improve system noise margin. Provides a reference voltage for the HSTL input buffer trip point. Output Impedance Matching Input: This input is used to tune the device outputs to the system data bus impedance. DQ output impedance is set to 0.2 x RQ, where RQ is a resistor from this ball to ground. Alternately, this ball can be connected directly to VDDQ to enable the minimum impedance mode. This ball cannot be connected directly to GND or left unconnected. DLL Disable: When LOW, this input causes the DLL to be bypassed for stable, low-frequency operation. Synchronous Data Inputs: Input data must meet setup and hold times around the rising edges of K and K# during WRITE operations. See Ball Assignment figures for ball site location of individual signals. The x8 device uses D0-D7. Remaining signals are NC. The x9 device uses D0D8. Remaining signals are NC. The x18 device uses D0-D17. Remaining signals are NC. The x36 device uses D0-D35. Remaining signals are NC. Synchronous Echo Clock Outputs: The edges of these outputs are tightly matched to the synchronous data outputs and can be used as data valid indication. These signals run freely and do not stop when Q tri-states. IEEE 1149.1 Test Output: 1.8V I/0 level.
R#
Input
W#
Input
BW_# NW_#
Input
K K#
Input
C C#
Input
TMS TDI TCK VREF ZQ
Input Input Input Input
DLL# D_
Input Input
CQ#, CQ
Output
TDO
Output
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
FBGA BALL DESCRIPTIONS (continued)
SYMBOL Q_ TYPE Output DESCRIPTION Synchronous Data Outputs: Output data is synchronized to the respective C and C# or to K and K# rising edges if C and C# are tied HIGH. This bus operates in response to R# commands. See Ball Assignment figures for ball site location of individual signals. The x8 device uses D0D7. The x9 device uses D0-D8. The x18 device uses Q0-Q17. Remaining signals are NC. The x36 device uses Q0-Q35. Remaining signals are NC. Power Supply: 1.8V nominal. See DC Electrical Characteristics and Operating Conditions for range. Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. 1.8V is also permissible. See DC Electrical Characteristics and Operating Conditions for range. Power Supply: GND. No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation.
VDD VDDQ VSS NC
Supply Supply Supply -
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
Figure 4 Bus Cycle State Diagram
RD
RD LOAD NEW READ ADDRESS READ DOUBLE always READ PORT NOP R_Init=0 /RD
/RD
Supply voltage provided
WT
POWER-UP
Supply voltage provided
WT LOAD NEW WRITE ADDRESS AT K# always WRITE DOUBLE AT K# WRITE PORT NOP /WT
/WT
NOTE: 1. The address is concatenated with one additional internal LSB to facilitate burst operation. The address order is always fixed as xxx . . . xxx + 0, xxx . . . xxx + 1. Bus cycle is terminated at the end of this sequence (burst count = 2). 2. State transitions: RD = (R# = LOW); WT = (W# = LOW). 3. Read and write state machines can be simultaneously active. 4. State machine control timing sequence is controlled by K.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
TRUTH TABLE
Notes 1-6 OPERATION WRITE Cycle: Load address, input write data on consecutive K and K# rising edges READ Cycle: Load address, output data on consecutive C and C# rising edges NOP: No operation STANDBY: Clock stopped K L(R)H R# X W# L D or Q DA(A + 0) at K(t) QA(A + 0) at C#(t + 1) D=X Q = High-Z Previous State D or Q DA(A + 1) at K#(t) QA(A + 1) at C(t + 2) D=X Q = High-Z Previous State
L(R)H
L
X
L(R)H Stopped
H X
H X
BYTE WRITE OPERATION
Notes 7, 8 OPERATION WRITE D0-17 at K rising edge WRITE D0-17 at K# rising edge WRITE D0-8 at K rising edge WRITE D0-8 at K# rising edge WRITE D9-17 at K rising edge WRITE D9-17 at K# rising edge WRITE nothing at K rising edge WRITE nothing at K# rising edge
NOTE: 1. X means "Don't Care." H means logic HIGH. L means logic LOW. means rising edge; means falling edge. 2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges, except if C and C# are HIGH, then data outputs are delivered at K and K# rising edges. 3. R# and W# must meet setup and hold times around the rising edge (LOW to HIGH) of K and are registered at the rising edge of K. 4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 5. Refer to state diagram and timing diagrams for clarification. 6. It is recommended that K = K# = C = C# when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 7. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation, provided that the setup and hold requirements are satisfied. 8. This table illustrates operation for the x18 devices. The x36 device operation is similar, except for the addition of BW2# (controls D18:D26) and BW3# (controls D27:D35). The x9 device operation is similar, except that BW1# and D8:D17 are not available. The x8 device operation is similar, except that NW0# controls D0:D3, and NW1# controls D4:D7.
K L(R)H
K# L(R)H
BW0# 0 0 0 0 1 1 1 1
BW1# 0 0 1 1 0 0 1 1
L(R)H L(R)H L(R)H L(R)H L(R)H L(R)H
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply Relative to VSS ........................................ 0.5V to +2.8V Voltage on VDDQ Supply Relative to VSS ....................................... -0.5V to +VDD VIN ..................................................... -0.5V to VDD + 0.5V Storage Temperature ..............................-55C to +125C Junction Temperature** ....................................... +125C Short Circuit Output Current .............................. 70mA
*Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. **Maximum junction temperature depends upon package type, cycle time, loading, ambient temperature, and airflow. See Micron Technical Note TN-05-14 for more information.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
0C TA +70C; +1.7V VDD +1.9V unless otherwise noted
DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Clock Input Signal Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage Supply Voltage Isolated Output Buffer Supply Reference Voltage CONDITIONS SYMBOL VIH(DC) VIL(DC) VIN ILI ILO VOH (LOW) VOH VOL (LOW) VOL VDD VDDQ VREF MIN VREF + 0.1 -0.3 -0.3 -5 -5 VDDQ - 0.2 VDDQ/2 - 0.12 VSS VDDQ/2 - 0.12 1.7 1.4 0.68 MAX VDDQ + 0.3 VREF - 0.1 VDDQ + 0.3 5 5 VDDQ VDDQ/2 + 0.12 0.2 VDDQ/2 + 0.12 1.9 VDD 0.95 UNITS V V V A A V V V V V V V NOTES 3, 4 3, 4 3, 4
0V VIN VDDQ Output(s) disabled, 0V VIN VDDQ (Q) |IOH| 0.1mA Note 1 IOL 0.1mA Note 2
3, 5, 7 3, 5, 7 3, 5, 7 3, 5, 7 3 3, 6 3
AC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
0C TA +70C; +1.7V VDD +1.9V unless otherwise noted
DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage
NOTE: 1. Outputs are impedance-controlled. |IOH| = (VDDQ/2)/(RQ/5) for values of 175W RQ 350W. 2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175W RQ 350W. 3. All voltages referenced to VSS (GND). 4. Overshoot: VIH(AC) VDD + 0.7V for t tKHKH/2 Undershoot: VIL(AC) -0.5V for t tKHKH/2 Power-up: VIH VDDQ + 0.3V and VDD 1.7V and VDDQ 1.4V for t 200ms During normal operation, VDDQ must not exceed VDD. Control input signals may not have pulse widths less than tKHKL (MIN) or operate at cycle rates less than tKHKH (MIN). 5. AC load current is higher than the shown DC values. AC I/O curves are available upon request. 6. Output buffer supply can be set to 1.5V or 1.8V nominal 0.1 with appropriate derating of AC timing parameters. Consult factory for further information. 7. HSTL outputs meet JEDEC HSTL Class I and Class II standards. 8. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC).
CONDITIONS
SYMBOL VIH AC) VIL(AC)
MIN VREF + 0.2 -
MAX - VREF - 0.2
UNITS V V
NOTES 3, 4, 8 3, 4, 8
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
13
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
IDD OPERATING CONDITIONS AND MAXIMUM LIMITS
0C TA +70C; VDD = MAX unless otherwise noted
MAX DESCRIPTION Operating Supply Current: DDR Standby Supply Current: NOP Stop Clock Current Output Supply Current: DDR (Information only) CONDITIONS Cycle time tKHKH (MIN); Outputs open KHKH = tKHKH (MIN); Device in NOP state; All addresses/data static Cycle time = 0; Input Static CL = 15pF
t
SYMBOL IDD (x8, x9, x18) (x36) ISB1 (x8, x9 x18) (x36) ISB IDDQ (x8, x9) (x18) (x36)
TYP TBD
-4
-5
-6
-7.5
UNITS mA
NOTES 1, 2, 3
All inputs VIL or VIH;
600 800 200 210 75 32 71 142
490 655 170 180 75 25 57 113
415 550 150 160 75 21 47 95
340 450 125 135 75 17 38 76
TBD TBD TBD
mA mA mA
2, 4 2 5
CAPACITANCE
DESCRIPTION Address/Control Input Capacitance Output Capacitance (Q) Clock Capacitance CONDITIONS SYMBOL CI TA = 25C; f = 1 MHz CO CCK TYP 4 6 5 MAX 5 7 6 UNITS pF pF pF NOTES 6 6 6
THERMAL RESISTANCE
DESCRIPTION Junction to Ambient (Airflow of 1m/s) Junction to Case (Top) Junction to Balls (Bottom)
NOTE: 1. 2. 3. 4. 5. IDD is specified with no output current. IDD is linear with frequency. Typical value is measured at 6ns cycle time. Typical values are measured at VDD = 1.8V, VDDQ = 1.5V, and temperature = 25C. Operating supply currents and burst mode currents are measured at 100 percent bus utilization. NOP currents are valid when entering NOP after all pending READ and WRITE cycles are completed. Average I/O current and power is provided for information purposes only and is not tested. Calculation assumes that all outputs are loaded with CL (in farads), f = input clock frequency, half of outputs toggle at each transition (for example, n = 18 for x36), CO = 6pF, VDDQ = 1.5V and uses the equations: Average I/O Power as dissipated by the SRAM is:
CONDITIONS Soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board
SYMBOL qJA qJC qJB
TYP 25 10 12
UNITS C/W C/W C/W
NOTES 6, 7 6 6, 8
P = 0.5 x n x f x VDDQ2 x (CL + 2CO). Average IDDQ = n x f x VDDQ x (CL + CO). 6. This parameter is sampled. 7. Average thermal resistance between the die and the case top surface per MIL SPEC 883 Method 1012.1. 8. Junction temperature is a function of total device power dissipation and device mounting environment. Measured per SEMI G3887.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS 1, 2, 3, 6, 8
0C TA +70C; +1.7V VDD +1.9V
DESCRIPTION SYMBOL -4 MIN MAX MIN -5 MAX MIN -6 MAX MIN -7.5 MAX UNITS
Clock Clock cycle time (K, K#, C, C#)4 Clock phase jitter (K, K#, C, C#)5 Clock HIGH time (K, K#, C, C#) Clock LOW time (K, K#, C, C#) Clock to clock# (K(R)K#, C(R)C#) at t KHKH minimum Clock to clock# (K#(R)K, C#(R)C) Clock to data clock (K(R)C, K#(R)C#) DLL lock time (K, C)6 K static to DLL reset Output Times C, C# HIGH to output valid C, C# HIGH to output hold C, C# HIGH to echo clock valid C, C# HIGH to echo clock hold CQ, CQ# HIGH to output valid7 CQ, CQ# HIGH to output hold7 C HIGH to output High-Z C HIGH to output Low-Z Setup Times Address valid to K rising edge8 Control inputs valid to K rising edge8 Data-in valid to K, K# rising edge8
t
KHKH
4.00
5.00 0.20
5.00
6.00 0.20
6.0
7.50 0.20
7.50
8.00 0.20
ns ns ns ns ns
t
KC var KHKL KLKH 1.60 1.60 1.80
t t t
2.00 2.00 2.20
2.40 2.40 2.70
3.00 3.00 3.38
KHK#H
t
K#HKH
t
1.80 0.00 1,024 30 0.40 -0.40 0.33 -0.33 0.35 -0.35 0.0 -0.40 0.40 0.40 0.40 1.80
2.20 0.00 1,024 30 0.43 -0.43 0.36 -0.36 0.38 -0.38 0.43 -0.43 0.50 0.50 0.50 2.30
2.70 0.00 1,024 30 0.45 -0.45 0.38 -0.38 0.40 -0.40 0.45 -0.45 0.60 0.60 0.60 2.80
3.38 0.00 1,024 30 0.45 -0.45 0.38 -0.38 0.40 -0.40 0.45 -0.45 0.70 0.70 0.70 3.55
ns ns cycles ns ns ns ns ns ns ns ns ns ns ns ns
KHCH lock
tKC t
KC reset
t t
CHQV CHQX
t t t
CHCQV CHCQX
CQHQV CQHQX
t
t
CHQZ
t
CHQX1 AVKH IVKH
t
t
t
DVKH
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
15
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS 1, 2, 3, 6, 8
0C TA +70C; +1.7V VDD +1.9V
DESCRIPTION SYMBOL -4 MIN MAX MIN -5 MAX MIN -6 MAX MIN -7.5 MAX UNITS
Hold Times K rising edge to address hold8 K rising edge to control inputs hold8 K, K# rising edge to data-in hold8
NOTE:
t
KHAX KHIX
0.40 0.40 0.40
0.50 0.50 0.50
0.60 0.70 0.60
0.70 0.70 0.70
ns ns ns
t
t
KHDX
1. Test conditions as specified with the output loading shown in Figure 5, unless otherwise noted. 2. Control input signals may not be operated with pulse widths less than tKHKL (MIN). 3. If C and C# are tied HIGH, K and K# become the references for C and C# timing parameters. 4. 5. 6. 7. The device will operate at clock frequencies slower than tKHKH (MAX). See Micron Technical Note TN-54-02 for more information. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. VDD slew rate must be less than 0.1V DC per 50ns for DLL lock retention. DLL lock time begins once VDD and input clock are stable. Echo clock is tightly controlled to data valid/data hold. By design, there is a 0.1ns variation from echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations. 8. This is a syncrhonous device. All addresses, data, and control lines must meet the specified setup and hold times for all latching clock edges.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
16
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
AC TEST CONDITIONS
Input pulse levels . . . . . . . . . . . . . . . . . . 0.25V to 1.25V Input rise and fall times . . . . . . . . . . . . . . . . . . . . 0.7ns Input timing reference levels . . . . . . . . . . . . . . . . 0.75V Output reference levels . . . . . . . . . . . . . . . . . . .VDDQ/2 ZQ for 50W impedance . . . . . . . . . . . . . . . . . . . . . 250W Output load . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 5
Figure 5 Output Load Equivalent
0.75V
VREF
VDDQ/2 50
SRAM
ZQ
Z O = 50
250
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
Figure 6 READ/WRITE Timing3
READ 1
K tKHKL K# tKLKH tKHKH tKHK#H
WRITE 2 3
READ 4
WRITE 5
READ 6
WRITE 7
NOP 8
WRITE (Note 2)
NOP 9 10
R# tIVKH W# tKHIX
(Note 3)
A A0 A1 A2 A3 A4 A5 A6
tAVKH tKHAX tAVKH tKHAX D D10 D11 D30 tDVKH D31 tKHDX D50 D51 tDVKH D60 tKHDX D61
(Note 1)
Q tCHQX1 tKHCH tKLKH tCHQV Q00 tCHQX Q01 tCHQX tCHQV Q20 tCQHQV Q21 Q40 Q41 tCHQZ
C
tKHKL tKHCH tKHK#H t KHKH
C# tCHCQV tCHCQX CQ tCHCQV tCHCQX CQ#
DON'T CARE
UNDEFINED
NOTE: 1. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0 + 1. 2. Outputs are disabled (High-Z) one clock cycle after a NOP. 3. In this example, if address A0 = A1, then data Q00 = D10, Q01 = D11. Write data is forwarded immediately as read results.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG)
The QDR SRAM incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-2001. The TAP operates using JEDEC-standard 1.8V I/O logic levels. The SRAM contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register.
1
Figure 7 TAP Controller State Diagram
TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 1 EXIT1-IR 0 0 PAUSE-IR 1 0 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1
Disabling the JTAG Feature
It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. Alternately, they may be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state, which will not interfere with the operation of the device.
1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0
TEST ACCESS PORT (TAP) Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.
NOTE:
The 0 or 1 next to each state represents the value of TMS at the rising edge of TCK.
Test Data-In (TDI)
The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see Figure 7. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most-significant bit (MSB) of any register, as illustrated in Figure 8.
Test MODE SELECT (TMS)
The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level.
Test Data-Out (TDO)
The TDO output ball is used to serially clock dataout from the registers. The output is active depending upon the current state of the TAP state machine. (See Figure 7.) The output changes on the falling edge of TCK. TDO is connected to the least-significant bit (LSB) of any register, as depicted in Figure 8.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
Figure 8 TAP Controller Block Diagram
0
Bypass Register
To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed.
Bypass Register
210
TDI
Selection Circuitry
Instruction Register
31 30 29 . . . 2 1 0
Selection Circuitry
TDO
Identification Register
x. . . . .210
Boundary Scan Register
The boundary scan register is connected to all the input and bidirectional balls on the SRAM. Several no connect (NC) balls are also included in the scan register to reserve balls. The SRAM has a 109-bit-long register. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the balls on the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
Boundary Scan Register
TCK TMS
TAP CONTROLLER
NOTE: X = 108 for all configurations.
Performing a TAP RESET
A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the ShiftDR state. The ID register has a vendor code and other information described in the Identification Register Definitions table.
TAP REGISTERS
Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK.
TAP INSTRUCTION SET Overview
Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described below in detail. The TAP controller used in this SRAM is fully compliant to the 1149.1 convention. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction regis-
Instruction Register
Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in Figure 8. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state, as described in the previous section. When the TAP controller is in the Capture-IR state, the two LSBs are loaded with a binary "01" pattern to allow for fault isolation of the board-level serial test data path.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
ter, and through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. The user must be aware that the TAP controller clock can only operate at a frequency up to 10 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture setup plus hold time (tCS plus tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE/PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the C and C#, and K and K#, captured in the boundary scan register. Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO balls.
EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary scan register cells at output balls are used to apply test vectors, while those at input balls capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the Update-IR state of EXTEST, the output drive is turned on and the PRELOAD data is driven onto the output pins.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board.
SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register.
RESERVED
These instructions are not implemented but are reserved for future use. Do not use these instructions.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
Figure 9 TAP Timing
1 Test Clock (TCK)
tMVTH
2
3
4
5
6
tTHTL tTHMX
t TLTH
tTHTH
Test Mode Select (TMS)
tDVTH tTHDX
Test Data-In (TDI)
tTLOV tTLOX
Test Data-Out (TDO) DON'T CARE UNDEFINED
TAP DC ELECTRICAL CHARACTERISTICS1,2
0C TA +70C; +1.7V VDD +1.9V
DESCRIPTION SYMBOL
t
MIN 100
MAX
UNITS ns
Clock
Clock cycle time Clock frequency Clock HIGH time Clock LOW time
t t
THTH
f
TF 40 40 0
10
MHz ns ns ns
THTL TLTH
Output Times
TCK LOW to TDO unknown TCK LOW to TDO valid TDI valid to TCK HIGH TCK HIGH to TDI invalid
t t t t
TLOX TLOV
20 10 10 10 10 10 10
ns ns ns ns ns ns ns
DVTH THDX
Setup Times
TMS setup Capture setup
t
MVTH
t
CS
Hold Times
TMS hold Capture hold
NOTE: 1. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in Figure 10.
t
THMX
t
CH
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
TAP AC TEST CONDITIONS
Input pulse levels . . . . . . . . . . . . . . . . . . . . . VSS to 1.8V Input rise and fall times . . . . . . . . . . . . . . . . . . . . . . 1ns Input timing reference levels . . . . . . . . . . . . . . . . . 0.9V Output reference levels . . . . . . . . . . . . . . . . . . . . . . 0.9V Test load termination supply voltage . . . . . . . . . . 0.9V
Figure 10 TAP AC Output Load Equivalent
0.9V 50 TDO Z O= 50 20pF
TAP DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
0C TA +70C; +1.7V VDD +1.9V unless otherwise noted
DESCRIPTION Input High (Logic 1) Voltage1,2 Input Low (Logic 0) Voltage1,2 Input Leakage Current Output Leakage Current Output Low Voltage1 Output Low Voltage1 Output High Voltage1 Output High Voltage1
NOTE: 1. 1All voltages referenced to Vss (GND). 2. Overshoot: VIH(AC) VDD + 0.7V for t tKHKH/2 Undershoot: VIL(AC) -0.5V for t tKHKH/2 Power-up: VIH VDDQ + 0.3V and VDD +1.7V and VDDQ 1.4V for t 200ms During normal operation, VDDQ must not exceed VDD. Control input signals (R#, W#, etc.) may not have pulse widths less than
t
CONDITIONS
SYMBOL VIH VIL
MIN 1.3 -0.3 -5.0 -5.0
MAX VDD + 0.3 0.5 5.0 5.0 0.2 0.4
UNITS V V A A V V V V
NOTES 1, 2 1, 2
0V VIN VDD Output(s) disabled, 0V VIN VDDQ (DQx) IOLC = 100A IOLT = 2mA IOHC = -100A IOHT = -2mA
ILI ILO VOL1 VOL2 VOH1 VOH1
1 1 1 1
1.6 1.4
KHKL (MIN) or operate at frequencies exceeding tKF (MAX).
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
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ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
IDENTIFICATION REGISTER DEFINITIONS
INSTRUCTION FIELD REVISION NUMBER (31:28) DEVICE ID (28:12) ALL DEVICES DESCRIPTION 000 Version number. 00def0Wx0t0q0b0s0 def = 001 for 36Mb density wx = 11 for x36, 10 for x18, 00 for x9, and 01 for x8 t = 1 for DLL version, 0 for non-DLL version q = 1 for QDR, 0 for DDR b = 1 for four-word burst, 0 for two-word burst s = 1 for separate I/O, 0 for common I/O 00000101100 Allows unique identification of SRAM vendor. 1 Indicates the presence of an ID register.
MICRON JEDEC ID CODE (11:1) ID Register Presence Indicator (0)
SCAN REGISTER SIZES
REGISTER NAME Instruction Bypass ID Boundary Scan BIT SIZE (x18) 3 1 32 109
INSTRUCTION CODES
INSTRUCTION EXTEST
1, 2
CODE 000 001 010 011 100 101 110 111
DESCRIPTION Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS
NOTE:
1. Data in output register is not guaranteed if EXTEST instruction is loaded. 2. After performing EXTEST, power-up conditions are required in order to return part to normal operation.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
24
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
BOUNDARY SCAN (EXIT) ORDER
BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 FBGA BALL 6R 6P 6N 7P 7N 7R 8R 8P 9R 11P 10P 10N 9P 10M 11N 9M 9N 11L 11M 9L 10L 11K 10K 9J 9K 10J 11J 11H 10G 9G 11F 11G 9F 10F 11E 10E BIT# 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 FBGA BALL 10D 9E 10C 11D 9C 9D 11B 11C 9B 10B 11A 10A 9A 8B 7C 6C 8A 7A 7B 6B 6A 5B 5A 4A 5C 4B 3A 2A 1A 2B 3B 1C 1B 3D 3C 1D BIT# 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 FBGA BALL 2C 3E 2D 2E 1E 2F 3F 1G 1F 3G 2G 1H 1J 2J 3K 3J 2K 1K 2L 3L 1M 1L 3N 3M 1N 2M 3P 2N 2P 1P 3R 4R 4P 5P 5N 5R INTERNAL
NOTE: For NC balls in the range of 1B-1P, 2B-2P, 3B-3P, 9B-9P, 10B-10P, and 11B-11P, a logic zero will be read from the chain. All other NC balls will appear in the scan chain as the logic level present on the ball site.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
25
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
Figure 11 165-Ball FBGA
0.850 0.075
SEATING PLANE C 0.12 C 10.00 1.00 TYP BALL A11
165X 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PREREFLOW DIAMETER IS O 0.40
BALL A1 PIN A1 ID
1.20 MAX
PIN A1 ID
1.00 TYP
14.00
17.00 0.10
7.00 0.05
8.50 0.10
5.00 0.05
7.50 0.05
MOLD COMPOUND: EPOXY NOVOLAC SUBSTRATE: PLASTIC LAMINATE SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or 62% Sn, 36% Pb, 2%Ag SOLDER BALL PAD: O .33mm
15.00 0.10
NOTE: 1. All dimensions are in millimeters.
DATA SHEET DESIGNATION
Advance: This data sheet contains initial descriptions of products still under development.
(R)
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron and the M logo are registered trademarks and SyncBurst and the Micron logo are trademarks of Micron Technology, Inc. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, Micron Technology, Inc., NEC, and Samsung.
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
26
(c)2002, Micron Technology Inc.
ADVANCE
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36 1.8V VDD, HSTL, QDRIIb2 SRAM
REVISION HISTORY
* Rev. A, Pub. 9/02..........................................................................................................................................................9/02 * New ADVANCE data sheet
36Mb: 1.8V VDD, HSTL, QDRIIb2 SRAM MT54W2MH18B_A.fm - Rev 9/02
27
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2002, Micron Technology Inc.

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